Recessed gate dielectric antifuse

ABSTRACT

A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and drain extension regions contiguous with the laterally spaced source and drain regions are optionally formed adjacent the recess. Programming of the recessed dielectric antifuse is performed by application of power to the gate and at least one of the source region and the drain region to breakdown the dielectric, which minimizes resistance between the gate and the channel.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device, and moreparticularly, to a recessed gate dielectric antifuse.

A conventional Metal Oxide Semiconductor Field Effect Transistor(MOSFET) comprises a doped polysilicon gate, a channel conductionregion, and source/drain regions formed by diffusion of dopants in thesilicon substrate. The channel region separates the source from thedrain in the lateral direction. A substantially planar layer of adielectric material that prevents electrical current flow separates thepolysilicon gate from the channel. The substantially planar dielectricmaterial separating the polysilicon gate from the channel region,henceforth referred to as the gate oxide, usually consists of thethermally grown silicon dioxide (SiO₂) material that leaks very littlecurrent through a mechanism, which is called Fowler-Nordheim tunnelingunder voltage stress.

A reliable, low resistance, programmable antifuse may be formed fromsuch a conventional MOSFET, which provides a high impedance between thegate and the source, the drain, the substrate, or a well. When theMOSFET is stressed beyond a critical electrical field by applyingsufficient voltage to the gate, the transistor is destroyed by rupturingthe gate oxide. In particular, the gate oxide over the substrate becomesa resistive short, causing part of the gate oxide to form current pathsby diffusion of polysilicon gate material or silicon from the substrate.

To increase device yield, semiconductor integrated circuits such asEPROMs, flash EEPROMs, DRAM, SRAM, and other various random accessmemory types employ redundant circuitry that allows the integratedcircuits to function despite the presence of one or more manufacturingor other defects by employing the redundant circuitry rather than theoriginal, defective circuitry. Such conventional memories often usegate-oxide antifuses as part of their redundancy scheme wherein theredundant circuitry may be employed in place of defective circuitry byblowing one or more of the antifuses.

To keep pace with the current trend toward maximizing the number ofcircuit devices contained in a single chip, integrated circuit designerscontinue to design IC devices with smaller and smaller feature sizes.

SUMMARY OF THE INVENTION

It is against the above mentioned background, that the present inventionprovides a number of unobvious advantages and advances over the priorart. In particular, the present invention discloses a recesseddielectric antifuse device and method of formation thereof. The antifusedevice includes a substrate and laterally spaced source and drainregions formed in the substrate. A recess is formed between the sourceand drain regions. A gate and gate oxide are formed in the recess andlightly doped source and drain extension regions contiguous with thelaterally spaced source and drain regions are optionally formed adjacentthe recess. Programming of the recessed dielectric antifuse is performedby application of power to the gate and at least one of the sourceregion and the drain region to breakdown the dielectric, which minimizesresistance between the gate and the channel.

BRIEF DESCRIPTION OF THE DRAWINGS

The aforementioned features and advantages of the present invention, aswell as additional features and advantages thereof, will be more clearlyunderstood hereinafter as a result of a detailed description of thevarious embodiments of the invention when taken in conjunction with thefollowing drawings, wherein like elements are indicated by like symbols.

FIG. 1 is a cross-sectional diagram illustrating a conventional MOSFETantifuse device.

FIGS. 2 and 3 schematically illustrate the cross sectional view ofvarious embodiments of an antifuse structure according to the presentinvention.

FIG. 4 is a flowchart illustrating a method to reduce on-stateresistance and improving current characteristics of the MOSFET antifusedevice, in according to embodiments of the present invention.

Skilled artisans appreciate that elements in the drawing are illustratedfor simplicity and clarity and have not necessarily been drawn to scale.For example, the dimensions of some of the elements in the drawing maybe exaggerated relative to other elements to help to improveunderstanding of the various embodiments of the present invention.

DETAILED DESCRIPTION OF THE VARIOUS EMBODIMENTS

The invention disclosed herein is directed to a recessed gate oxideantifuse and a method of fabricating the recessed gate oxide antifusestructure. The drawing figures illustrate a partially completedintegrated circuit device. In the following description, numerousdetails are set forth in order to provide a thorough understanding ofthe present invention. It will be appreciated by one skilled in the artthat variations of these specific details are possible while stillachieving the results of the present invention.

Additionally, well-known processing steps are not described in detail inorder not to unnecessarily obscure the present invention. For the sakeof brevity, conventional electronics, semiconductor manufacturing,memory technologies and other functional aspects of the devices (andcomponents of the individual operating components of the devices) maynot be described in detail herein. Furthermore, for purposes of brevity,the invention is frequently described herein as pertaining to anantifuse for use in electrical or electronic systems.

It should be appreciated that many other manufacturing techniques couldbe used to create the antifuses described herein, and that thetechniques described herein could be used as individual devices, groupedtogether in discrete circuits, formed in memory arrays, or integratedwith other devices. Further, the techniques would be suitable forapplication in electrical systems, optical systems, consumerelectronics, industrial electronics, wireless systems, appliances, spaceapplications, or any other application.

The term antifuse and the terms storage or programmable coupled with theterms cell, element, or device are often used interchangeably in thisfield. The present invention is applicable to all these terms as theyare generally understood in the relevant art.

The terms chip, integrated circuit, monolithic device, semiconductordevice and microelectronic device are often used interchangeably in thisfield. The present invention is applicable to all of these terns as theyare generally understood in the field.

The terms pins, pads and leads refer to input and/or output terminals ofa connector, device, chip, printed circuit, or the like, which are usedto provide electrical connection to one or more connectors, devices,chips, printed circuits, or the like. The present invention isapplicable to all of these terms as they are generally understood in thefield.

The terms metal line, trace, wire, conductor, signal path and signalingmedium are all related. These related terms are generallyinterchangeable and appear in order from most specific to most general.In this field, metal lines are sometimes referred to as traces, wires,lines, interconnect or simply metal. Metal lines, generally aluminum(Al) or an alloy of Al and copper (Cu), are conductors which providesignal paths for coupling, or interconnecting, electrical circuitry.Conductors other than metal are available in microelectronic devices.Materials such as doped polysilicon, doped single-crystal silicon (oftenreferred to simply as diffusion, regardless of whether such doping isachieved by thermal diffusion or ion implantation), titanium (Ti),molybdenum (Mo), or refractory metal silicides are examples of otherconductors. Signaling medium is the most general term and encompassesthe others.

Moreover, it should be understood that the spatial descriptions (e.g.,“above”, “below”, “up”, “down”, “top”, “bottom”, “beneath”, “across”,etc.) made herein are for purposes of illustration only, and thatpractical antifuses can be spatially arranged in any orientation ormanner. Arrays of these antifuses can also be formed by connecting themin appropriate ways and with appropriate devices.

As discussed below, the following sections more fully describe thepresent invention.

A cross-sectional view of a conventional MOSFET device 100 is shown inFIG. 1 to illustrated the differences of the present invention from theprior art. MOSFET 100 comprises a a gate dielectric 110 overlaid with agate 112 and formed on a substrate 114. The gate 112 is typically formedof polysilicon, and the gate dielectric 110 is typically a gate oxide,such as for example, silicon dioxide, silicon nitride, or the like.

Within the substrate 114 are formed heavily doped source and drainregions 116 and 118, and lightly-doped source and drain extensionregions 120 and 122, respectively. Generally, doped regions are regionscontaining a higher concentration of p-type or n-type dopants than therest of the substrate 114. The source and drain extension regions 120and 122 generally have a lower concentration of dopants compared to thesource and drain regions 116 and 118. However, the regions 116, 118, 120and 122 can be doped to the same levels. The region in the substratedirectly below the gate 112, and between source and drain extensionregions 120 and 122, is typically referred to as a channel region 124.

Resistive current paths can be formed between the gate 112, the channelregion 124, or the source and drain extension regions 120 and 122. Thelowest resistance paths tend to be between the gate 112 and the sourceor drain regions 116 and 118 and the source or drain extension regions120 and 122. However, when the resistive current paths are formed fromthe gate electrode 112 to the substrate 114, which can comprise a P-wellor N-well, the fuse resistance is much higher. It is known by thosehaving ordinary skilled in the art that soft breakdown (i.e., high fuseresistance) and hard breakdown (i.e., low fuse resistance) areinfluenced by a breakdown spot position. The soft breakdowns almostexclusively occur between the gate 112 and channel region 124 (i.e.,substrate, N-well, or P-well).

Both high resistance and low resistance breakdown paths are illustratedin FIG. 1. Breakdown of the gate dielectric 110 is caused by applicationof a voltage (Vg) to gate 112, while source 116 and drain 118 aregrounded. Generally, programming and sensing of antifuse devices, andthe associated circuits to perform these operations, are well known topersons having ordinary skill in the art. Metal lines, polysilicon dopedregions, or the like, are used to couple the drain and source regions toground for programming, or to a sense circuit for determining the stateof the antifuse.

For antifuse applications, the soft breakdowns are undesirable becausefuse resistance distribution is considerably higher than that of thehard breakdown. Also, the fuse resistance of the conventional MOSFETantifuse device initially decreases in channel length, but begins toincrease with a further decrease in channel length for a given powersupply applied to the antifuse. Furthermore, the variability of the fuseresistance increases with a decrease in channel length. In particulartechnologies, in order to achieve a high density memory cell, the fusestructure should be as small as possible. Thus, conventional MOSFETantifuse devices are not suitable to provide for a small redundancy orerror correction structure of a high density memory cell due tovariability of the fuse resistance and increase in fuse resistance.

The present invention is directed to a device and associatedmanufacturing method that overcome these above-noted deficiencies inconventional MOSFET antifuses.

FIG. 2 illustrates a cross-section of a MOSFET antifuse device 200according to an embodiment of the present invention. Antifuse 200 isfabricated on a silicon substrate 210 of a first conductivity type. Thesubstrate 210 can be any semiconductor material, including, for example,gallium arsenide (GaAs), silicon (Si), strained silicon, germanium (Ge),silicon-germanium (SiGe), silicon-on-insulator (SOI),silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxiallayers of silicon supported by a base semiconductor foundation, andother semiconductor structures. In the illustrated embodiment, thesubstrate is P-type silicon having a resistivity of from about 1 to 100ohms/cm.

After defining shallow trench isolation (STI) regions, the substrate 210is patterned to form recess regions in the active areas, such as forexample, a recess 212 formed in the substrate 210. Width of the recess212 is about 0.5 times the wordline width. Depth of recess 212 isadjusted to optimize electrical characteristics of the access device.Next a sacrificial oxide/wet etch oxide 213 for surface smoothing isgrown in the recess 212. This sacrificial oxidation is optimized tominimize a thickness delta between the bottom and the sidewall of therecess 212.

A gate dielectric layer 214 is formed over the surface of substrate 210,lining the recess 212, using conventional semiconductor processingtechniques, thereby forming a recessed gate dielectric. In oneembodiment, the gate dielectric layer 214 is an oxide, such as forexample, silicon dioxide, and has a thickness of between about 20 andabout 50 angstroms. In one embodiment, the gate oxide 214 is grown withthe oxidation again being optimized to minimize a thickness deltabetween the bottom and the sidewall of the recess 212. The gate oxide214 is then patterned (e.g., photo/etch) as needed to define thin/thickoxide regions.

The present invention, however, is not limited to antifuses having oxidedielectrics. Those of ordinary skill in the art will be able tosubstitute other known antifuse dielectric materials into the antifusestructure disclosed herein. For example, in other embodiments, amorphoussilicon, silicon nitride, ONO, tantalum oxide (Ta₂O₅), BST, PZT,lanthanide materials, and combinations thereof may be a suitabledielectric. Additionally, the dielectric thickness will, in part,determine the voltage at which programming of the antifuse element willbe achieved. Proper selection of the thickness will assure bothunprogrammed antifuse integrity and that the program voltage will be lowenough such that an integrated circuit process can be used to build anarray using the antifuse element.

An optional second gate oxidation may be performed to provide a desiredgate oxide 214 thickness for access and periphery thick oxide devices.Once again, the second gate oxidation is optimized to minimize thicknessdelta between bottom of recess and sidewall of recess.

Next, a gate 216 is formed on the surface of dielectric layer 214, whereby the thickness of the deposition completely fills the recess 212. Thegate 216 is doped, in-situ or via implantation, to provide poly dopants(n+poly, p+poly), a desired threshold voltage, sheet resistance, and thelike. In one embodiment, gate 216 is an amorphous silicon having athickness of about between 1,500 and 3,000 angstroms, and doped to asheet resistance of about 30 ohms/square. The gate 216 is defined usingconventional processing techniques where by the remaining exposed gateoxide may be removed using standard semiconductor etching techniques. Inother embodiments, the gate 216 may be metal, silicon, polysilicon,polycide, silicide, and combinations thereof. Rapid thermal processing(RTP) is then performed to active the poly dopants.

After gate 216 is defined, optionally, first and second lightly dopedextension regions 218 and 220 of a second conductivity type are formedin substrate 210 using the well-known self-aligned gate process. In oneembodiment, the first and second regions 218 and 220 are lightly dopedsource and drain (LDD) regions formed in the substrate 210 adjacent thechannel region. In the illustrated embodiment, the lightly doped drain(LDD) are n− regions formed by implanting ions, selected fromphosphorus, arsenic, and antimony ions, at energies within ranges thatare conventional in the art to achieve a selected source and drainimpurity ion amount. Typically, ions are implanted with dosages of frombetween about 1×10¹³ to about 1×10⁴ atoms/cm² at energies of betweenabout 5 to 80 KeV at a vertical angle to provide an average dopantconcentration for the LDD regions ranging from about 1×10¹⁷ ions/cm³ to1×10¹⁹ ions/cm³. For LDD p− regions, boron, boron bifluoride (BF₂), orborane (B₂H₁₀) ions are used with the same dosages and energies, andresulting in the same concentrations as mentioned above.

Spacers 222 and 224 are then formed on the sidewalls of gate 216 and inone embodiment, are formed by providing a layer of CVD SiO₂ and etchingit back, leaving spacers 222 and 224. In other embodiments, the spaces222 and 224 may be silicon nitride, or any other suitable spacermaterial. The spacers 222 and 224 may have a base width from about 100to about 500 Angstrom. In another embodiment, an insulating cappinglayer 225, integral with spacers 222 and 224 may formed and having athickness of between from about 100 to about 200 Angstroms. The cappinglayer 225 may be the same material as the spacers 222 and 224, or anyother suitable insulating material.

Third and fourth regions 226 and 228 of the second conductivity type arethen formed in the silicon substrate 210 using known methods. In oneembodiment, regions 226 and 228 are heavily doped source and drain (HDD)regions formed by the ion implantation of n+ ions. Ions selected fromphosphorus, arsenic, antimony ions and the like are implanted atenergies within ranges that are conventional in the art to achieve aselected source and drain impurity ion amount. Typically, n+ ions areimplanted at dosages of between about 1×10¹⁴ to about 8×10¹⁵ atoms/cm²,and at energies of between about 5 to about 80 KeV at a vertical angleto provide an average dopant concentration for the diffusion regionsranging from about 1×10¹⁷ ions/cm³ to 1×10¹⁹ ions/cm³. For HDD p+regions, boron, boron bifluoride (BF₂), or borane (B₂H₁₀) ions are usedwith the same dosages and energies, and resulting in the sameconcentrations as mentioned above. Regions 226 and 228 are self alignedto the edges of spacers 222 and 224. Regions 226 and 228 are so locatedthat region 226 is contiguous with region 218 and region 228 iscontiguous with region 220.

Next, an insulating region 230 may be formed. Contact holes are thenetched in insulating region 230 and contacts 232 and 234 are formed toregions 226 and 228 and contact 236 is formed to gate 216. Contacts 232,234 and 236 are used to form electrical connections to a metal layer forconnection to other circuitry in the integrated circuit as is well knownin the art. In one embodiments, the contacts 232, 234, and 236 may be ametal, titanium tungsten (TiW), polysilicon, and combination thereof.

Before programming, antifuse 200 is an open circuit, the resistancebetween gate 216 and the regions 218, 220, 226, and 228 in the siliconsubstrate 210 being higher than 1×10⁹ ohms. A low resistance filament238 may be formed between regions 220 and/or 228 and the gate 216 byapplying a programming voltage in the range of 6-8 volts on region 228with respect to the substrate, with region 226 held at the substratepotential while the gate 216 is grounded or biased at a slightlypositive voltage, i.e., a voltage in the approximate range of 0-2 volts,with respect to the substrate. All voltages are measured with respect tothe substrate.

Under these conditions, the device will be brought into snap-backbreakdown. Snap-back breakdown is a well known phenomenon, characterizedin the structure of FIG. 2 by turning on the parasitic NPN bipolartransistor having regions 218 and 226 as its emitter, substrate 210 asits base, and regions 220 and 228 as its collector. Snap-back breakdownis further characterized by a rise in the current flowing into regions220 and 228 and by a high-electric-field existing at or near thejunction between regions 220 and 228 and substrate 210. The combinationof high current density and high electric field results in thegeneration of holes through avalanche-impact ionization and subsequentacceleration of these holes. Some of the energetic holes (or hot holesas they are commonly called) are injected into the dielectric 214. It isknown that hole injection into a dielectric, such as SiO₂, causes oraccelerates the dielectric breakdown process.

Under the snap-back breakdown condition, dielectric 214 in the antifuse200 can be broken down in milliseconds or a shorter time. Afterbreakdown, contact 236 will be electrically connected to contact 234through gate 216, with an ohmic connection through the rupture indielectric 214 located over regions 220 and/or 228. Thus, the antifuseis programmed.

It is to be appreciated that regions 218 and 220 are optional.Accordingly, if the structure disclosed with respect to FIG. 2 did notinclude lightly doped regions 218 and 220, rupture of gate dielectric214 would tend to short contact 236 and gate 216 to not only region 228but also to substrate 210 because the high electric field would belocated at the metallurgical junction between the substrate 210 and theheavily-doped drain 228. Since substrate 210 is held at ground, nouseful electric signal could be passed from contact 234, through gate216 and region 228, to contact 236. The antifuse in FIG. 2 is immune tothis problem. Depending on the LDD dose, the high electric field can bemoved inside the n− region, thus preventing breakdown to substrate 210and guaranteeing breakdown into the doped region in the substrate. Otherknown techniques for fabricating the n− region of an LDD structure,including those not using spacers 222 and 224, may of course beemployed.

Referring now to FIG. 3, a cross sectional diagram of an array ofantifuses of FIG. 2 is shown. FIG. 3 is illustrative only and depicts asingle row of an array having two antifuses. Those of ordinary skill inthe art will readily realize that actual arrays fabricated according tothe present invention may have an arbitrary number of rows.

Field oxide regions separate the pair of antifuses 310 a and 310 b fromother antifuse pairs on the same row as is conventionally employed inintegrated circuit layout design. Antifuses 310 a and 310 b share acommon source 326 and are each identical to the antifuse described withreference to FIG. 2, and the description thereof will not be repeated inorder to avoid a repetitious disclosure. Contact 336 a to polysilicongate 316 a and its associated metal line, shown in cross section, form afirst column line for the array and contact 336 b to polysilicon gate316 b and its associated metal line, shown in cross section, form asecond column line for the array. Contacts 334 a and 334 b are connectedtogether to a row line, shown schematically as a wire 340.

As shown in FIG. 3, only antifuse 310 b has been programmed and containsa conductive filament 338. Antifuse 310 b remains unprogrammed.

FIG. 4 illustrates a flow chart showing a method 400 for reducingon-state resistance and improving current characteristics of an antifusedevice, according to embodiments of the present invention. At step 402,a substrate is provided, which can be a lightly doped substrate. At step404, a recess having a predetermined geometry (depth and lateralextensions) is formed in the substrate, and at step 406, the recess islined with a gate dielectric, forming a recessed gate dielectric. Atstep 408, a gate is formed on the recessed gate dielectric filling therecess. At step 410, laterally spaced lightly doped source and drainextension regions are optionally formed adjacent the gate. At step 412,spacers are formed on sidewalls of the gate, and if provided overlyingthe lightly doped source and drain extension regions. At step 414,heavily doped source and drain regions are formed, which are contiguouswith the laterally spaced lightly doped source and drain extensionregions, if provided. At step 416, contacts are formed. At step 418, theantifuse device is programmed.

As illustrated by FIG. 2, the gate dielectric 214 and gate 216 arenon-planar or curvilinear, as opposed to planar or linear as illustratedby FIG. 1. Accordingly, a recessed channel is defined between the sourceand drain regions, which has a longer length in a smaller area thanconventional planar gates.

An advantage of the present invention is the compact nature ofnonvolatile one-time programming antifuse devices, which can bemanufactured using standard 0.13 μm or other CMOS processes.Additionally, the present invention with its recessed gate dielectricarrangement, provides in one embodiment about a 20 percent reduction ingate oxide thickness, and about a 25 percent reduction in gate thicknessas compared to conventional gate-oxide antifuses. Furthermore, thepresent invention provide a longer gate length in a smaller horizontalarea, such that programming can use a lower voltage than theconventional programming voltages of 10 to 12 volts used to rupture thegate oxide. Moreover, the antifuse devices of the present inventionminimize resistance variances between blown antifuse devices and areoptimized with small chip area utilization. Thus, integrating multitudesof antifuses on a single IC can be achieved according to the presentinvention.

The present invention can be implemented with various changes andsubstitutions to the illustrated embodiments. For example, the presentinvention can be useful in programmable application-specific integratedcircuits (ASICs), such as programmable logic devices (PLDs) andfield-programmable gate arrays (FPGAs).

The above described embodiments are intended to illustrate theprinciples of the invention, not to limit its scope. Other embodimentsin variations to these preferred embodiments will be apparent to thoseskilled in the art and may be made without departing from the spirit andscope of the invention as defined in the following claims.

1. A method of fabricating at least one antifuse structure of asemiconductor memory device, comprising: providing a substrate having afirst surface; forming a recess in said substrate, said recess extendingdown from said first surface; forming a dielectric layer on saidsubstrate lining said recess, said dielectric layer having a surfacerecessed below said first surface; forming a gate overlaying the surfaceof said dielectric layer and filling said recess, said gate havingsidewalls; forming spacers at least on said sidewalls of said gate;forming source and drain regions adjacent said sidewalls; and formingcontacts to said gate and at least one of said source and drain regions.2. The method of claim 1, wherein said source and drain regions areheavily doped and said method further comprising forming lightly dopedsource and drain extension regions contiguous with said heavily dopedsource and drain regions.
 3. The method of claim 1, wherein said gatehas a thickness of about 1500 to about 3000 angstroms.
 4. The method ofclaim 1, wherein said gate is selected from the group comprising metal,amorphous silicon, silicon, polysilicon, polycide, silicide, andcombinations thereof.
 5. The method of claim 1, wherein said dielectriclayer has a thickness of about 20 to about 50 Angstroms.
 6. The methodof claim 1, wherein said dielectric layer is selected from the groupcomprising oxides, silicon dioxide, silicon nitride (SiN_(x)), amorphoussilicon, ONO, tantalum oxide (Ta₂O₅), BST, PZT, lanthanide materials,and combinations thereof.
 7. The method of claim 1, wherein saidcontacts are formed of a material selected from the group comprisingmetals, titanium tungsten (TiW), polysilicon, and combination thereof.8. The method of claim 1, wherein said source and drain regionscomprises n+ ions.
 9. The method of claim 1, wherein said source anddrain regions comprises p+ ions.
 10. The method of claim 1, furthercomprising doping said gate.
 11. The method of claim 1, furthercomprising programming said antifuse structure to form a low resistancefilament.
 12. A method of fabricating at least one antifuse structure ofa semiconductor memory device, comprising: providing a substrate havinga first surface; forming a recess in said substrate, said recessextending down from said first surface; forming a dielectric layer onsaid substrate lining said recess, said dielectric layer having asurface recessed below said first surface; forming a gate overlaying thesurface of said dielectric layer, said gate having sidewalls; forminglightly doped source and drain extension regions adjacent said gate;forming spacers at least on said sidewalls of said gate and overlayingsaid lightly doped source and drain extension regions; and formingheavily doped source and drain regions contiguous with said lightlydoped source and drain extension regions.
 13. The method of claim 12,wherein said gate has a thickness of about 1500 to about 3000 angstroms.14. The method of claim 12, wherein said gate is selected from the groupcomprising metal, silicon, amorphous silicon, polysilicon, polycide,silicide, and combinations thereof.
 15. The method of claim 12, whereinsaid dielectric layer has a thickness of about 20 to about 50 Angstroms.16. The method of claim 12, wherein said dielectric layer is selectedfrom the group comprising oxides, silicon dioxide, silicon nitride(SiN_(x)), amorphous silicon, ONO, tantalum oxide (Ta₂O₅), BST, PZT,lanthanide materials, and combinations thereof.
 17. The method of claim12, wherein said contacts are formed from a material selected from thegroup comprising metals, titanium tungsten (TiW), polysilicon, andcombinations thereof.
 18. The method of claim 12, wherein said heavilydoped source and drain regions comprises ions selected from phosphorus,arsenic, antimony, boron, boron bifluoride (BF₂), borane (B₂H₁₀), andcombinations thereof, and which are implanted at dosages of betweenabout 1×10¹⁴ to about 8×10¹⁵ atoms/cm², and at energies of between about5 to about 80 KeV at a vertical angle to provide an average dopantconcentration in said heavily doped source and drain regions rangingfrom about 1×10¹⁷ ions/cm³ to 1×10¹⁹ ions/cm³.
 19. The method of claim12, wherein said lightly doped source and drain extension regionscomprises ions selected from phosphorus, arsenic, antimony, boron, boronbifluoride (BF₂), borane (B₂H₁₀), and combinations thereof, and whichare implanted at dosages of from between about 1×10¹³ to about 1×10¹⁴atoms/cm², and at energies of between about 5 to 80 KeV at a verticalangle to provide an average dopant concentration in said lightly dopedsource and drain extension regions ranging from about 1×10¹⁷ ions/cm³ to1×10¹⁹ ions/cm³.
 20. The method of claim 12, further comprising dopingsaid gate.
 21. The method of claim 12, further comprising programmingsaid antifuse structure to form a low resistance filament between saidlightly doped extension regions and/or heavily doped source and drainregions and said gate.
 22. A method for reducing on-state resistance andimproving current characteristics of an antifuse device, comprising:providing a substrate; forming a recess in said substrate; lining saidrecess with a gate dielectric, thereby forming a recessed gatedielectric; filling said recess by forming a gate on said recessed gatedielectric; optionally forming laterally spaced lightly doped source anddrain extension regions adjacent said gate; forming spacers on sidewallsof said gate, and if provided, said spacers overlay said lightly dopedsource and drain extension regions; forming laterally spaced heavilydoped source and drain regions which are contiguous with said laterallyspaced lightly doped source and drain extension regions, if provided;and forming contacts with said gate and at least one of said heavilydoped source and drain regions.
 23. An antifuse device, comprising: asubstrate; a source region laterally spaced from a drain region having arecess there between; a gate dielectric formed in said recess; and agate formed on said gate dielectric, whereby programming of the antifuseis performed by application of power to said gate and one of said sourceregion and said drain region to break-down said gate dielectric.
 24. Theantifuse device as recited in claim 23, wherein said power impresses avoltage on said gate and said at least one of said source region andsaid drain region.
 25. The antifuse device according to claim 23,wherein said source and drain regions receive a same amount of voltageduring said programming.
 26. The antifuse device as recited in claim 23,wherein said source and drain regions are heavily doped with N-typematerial.
 27. The antifuse device as recited in claim 23, wherein saidsource and drain regions are heavily doped with P-type material.
 28. Theantifuse device according to claim 23, further comprises lightly dopedsource and drain extension regions formed contiguous with said sourceand drain regions.
 29. The antifuse device according to claim 23,wherein said substrate is doped with P-type material.
 30. The antifusedevice according to claim 23, wherein said substrate is formed oflightly doped P-type material.
 31. The antifuse device as recited inclaim 23, further comprises spaces formed on sidewalls of said gate, andlightly doped source and drain extension regions overlap under saidspacers, said lightly doped source and drain extension regions arecontiguous with said source and drain regions.
 32. An antifuse device,comprising: a substrate; a recess formed between laterally spaced sourceand drain regions that are formed in said substrate; a gate oxide formedin said recess; a gate formed on said gate oxide; and lightly dopedsource and drain extension regions formed contiguous with said sourceand said drain regions, whereby programming of the antifuse is performedby application of power to said gate and one of said source region andsaid drain region to break-down said gate oxide.
 33. An antifuse device,comprising: a substrate; a source region laterally spaced from a drainregion having a recessed gate oxide there between; a gate formed on saidrecessed gate oxide, said gate having sidewall spacers above saidrecessed gate oxide.
 34. An antifuse structure, comprising: asemiconductor substrate of a first conductivity type having a firstsurface and a recess; an insulating layer having a portion providedbelow said first surface lining said recess; a conductive gate disposedover said insulating layer and filling said recess, said conductive gatehaving outer edges above said first surface of said semiconductivesubstrate; spacers disposed at said outer edges of said conductive gate;spaced-apart first and second lightly doped regions of a secondconductivity type disposed in said semiconductor substrate, said firstand second lightly doped regions aligned to said outer edges of saidconductive gate; third and fourth more heavily doped regions of thesecond conductivity type disposed in said semiconductor substrate, saidthird and fourth regions contiguous with said first and second regions,respectively, and aligned to said outer edges of said spacer elements;and a conductive filament in said insulating layer, said conductivefilament connecting said conductive gate to one of said second andfourth doped regions.
 35. A method for creating said conductive filamentin an antifuse structure as defined in claim 34, comprising: biasingsaid first region and said semiconductor substrate at a first potential;biasing said gate at a second potential, said second potential being inthe range of about 0-2 more volts positive than said first potential;applying a third potential to said fourth region, said third potentialbeing more positive than said first potential in an amount sufficient tocause snap-back breakdown of said antifuse structure.
 36. An array ofantifuse structures arranged as a matrix of a plurality of rows andcolumns, each of said antifuse structures fabricated on the samesemiconductor substrate of a first conductivity type having a firstsurface and a recess, and including an insulating layer having a portionprovided below said first surface lining said recess, a conductive gatedisposed over said insulating layer and filling said recess, saidconductive gate having outer edges above said first surface of saidsemiconductive substrate, spacer elements disposed at the outer edges ofsaid conductive gate, said spacer elements having outer edges,spaced-apart first and second lightly doped regions of a secondconductivity type disposed in said semiconductor substrate, said firstand second lightly doped regions aligned to said outer edges of saidconductive gate, third and fourth more heavily doped regions of thesecond conductivity type disposed in said semiconductor substrate, saidthird and fourth more heavily doped regions contiguous with said firstand second lightly doped regions, respectively, and aligned to saidouter edges of said elements, said array further including: a pluralityof row lines running in a first direction, each of said row lines,corresponding to one of said plurality of rows, electrically connectedto the said second regions of a plurality of said antifuse structuresassociated with said one of said plurality of rows, and a plurality ofcolumn lines running in a second direction, each of said column lines,corresponding to one of said plurality of columns, electricallyconnected to the said conductive gates of a plurality of said antifusestructures associated with said one of said plurality of columns.